Operational amplifiers (op-amps) in general, and particularly voltage regulators are circuits that provide analog voltages, generally in integrated circuits, such as memory circuits. In many cases, op-amps provide an output voltage, which is a fixed multiple of an input or reference voltage. In the general case, this input voltage may be a signal whose voltage changes with time, while in the case of a voltage regulator, the input is generally at a fixed DC level.
FIG. 1 illustrates a simple, prior art op-amp 7, well known in the art. A differential stage GM1 provides a voltage output for a differential voltage input. The differential stage GM1 receives an input voltage Vref at one of its inputs (the negative input in the illustration). The output PG of differential stage GM1 is connected to the input or gate (designated “g” in FIG. 1) of a PMOS (p-channel metal oxide semiconductor) transistor M1, which serves as an inverting gain stage or inverting stage. The supply terminal or source of transistor M1 (designated “s” in FIG. 1) is connected to positive voltage supply Vdd. The output or drain terminal of transistor M1 (designated “d” in FIG. 1) is connected to a current load element I1 via a node 5. In FIG. 1, I1 is a resistive voltage divider, but in the general case it may be any element that draws current, such as but not limited to, a transistor, current source, diode, etc. The output of transistor M1 is designated as OP and is also the output OP of op-amp 7. The output OP is also connected to a capacitive load CL. The output of the current load element I1 is connected to the second input (the positive input in the illustration) of differential stage GM1 as its feedback FB. The feedback in op-amp 7 may equalize the two inputs to differential stage GM1, and accordingly, the output OP is at a voltage determined by the resistor ratio in current load element I1. Unlike the well-known Miller architecture, op-amp 7 does not contain a compensating capacitor between the gate and drain of transistor M1, but rather relies on the large output capacitor CL for stability. Part of the stability condition is that transistor M1, i.e., the inverting stage, should be a weak transistor. This means that transistor M1 should have a low current driving capability, or transconductance, gm. In addition, differential stage GM1 should be a strong stage, having a large gm. This type of architecture is very common in flash and other memory integrated circuits, where it is important to regulate voltage on very large capacitors (50 pF-200 pF typically).
During steady-state conditions, the currents in transistor M1 and current load element (e.g., resistor divider) I1 are essentially equal, and the output has reached its final value. When the op-amp 7 is turned on, or when the input voltage is changed, the feedback action causes the current in transistor M1 to either increase or decrease, as is appropriate, thereby to ramp output OP to a new steady state. During these transient conditions, the input voltage of transistor M1 may be driven to either the positive (Vdd) or negative (GND) supply rails. Enabling of the regulator and a fast ramp to the steady state value of output OP are of particular interest in voltage regulator applications. Output OP is usually grounded before the op-amp 7 is turned on and needs to be driven to a high positive value quickly. During the transient condition, the input voltage of transistor M1 may be driven to GND.
In general, the current (ID) in transistor M1 is defined by:                     ID        =                  k          ⁢                      W            L                    ⁢                      (                          Vgs              -              Vt                        )                                              (        1        )            
where k is a constant, Vgs is the gate-source voltage, Vt is the threshold voltage and W, L are the dimensions of the transistor. During transient conditions, current ID may be several times that of steady-state conditions. As mentioned earlier, in this op-amp architecture, transistor M1 is the weaker stage, and thus is the limiting factor for the fast-ramp to a final output OP.
FIG. 2 illustrates a similar op-amp architecture to that illustrated in FIG. 1. The architecture of FIG. 2 differs from that of FIG. 1 in that the differential stage GM1 and the transistor M1 have Vdd as their positive supply, while the output OP is at a different (preferably higher) supply, Vpp. The current from transistor M1 is mirrored to the output by cascaded current mirrors, comprising transistors M3A-M3B and M4A-M4B.
Transistors M3A and M3B may be NMOS (n-channel metal oxide semiconductor) transistors, whereas transistors M4A and M4B may be PMOS transistors. As is known in the art, a current mirror receives a current at its input, and sources or sinks an identical or multiplied current at its output. Transistor M1 provides current to the connected gate/drain of transistor M3A. Transistor M3B is matched to transistor M3A, having the same, or multiplied dimensions, and since it has the same Vgs voltage, its output current will be identical to (or multiplied by) that of transistor M3A, as in equation (1). This current is further mirrored to OP by the M4A-M4B current mirror. In short, the level of transistor M1 is shifted to the higher voltage level at output OP such that the output OP may be as high as the Vpp supply. This is accomplished by current mirrors, which provide a current path to the OP node.
During the turn-on of the op-amp of FIG. 2, it is desired to achieve a fast ramp of output OP to its steady state value. Assuming typical values wherein Vdd=1.8V, Vpp=10V, Vt=1V and CL=100 pF, the ramping of OP may be limited by the transistor M1 current on the output capacitor CL. As mentioned earlier, transistor M1, i.e., the inverting stage, needs to be a weak stage, and since its supply span is small, the difference between its transient current and steady state current is also small (for example a factor of 2), and thus under these conditions, the OP voltage may rise slowly.
FIG. 3 illustrates another version of a prior-art circuit. In this case, the output of transistor M4B is buffered to output OP. This may be accomplished by connecting the output (drain) of transistor M4B to a capacitor C1 and to an NMOS transistor M5, which is configured as a source follower. The main difference between the configuration of FIG. 3 and of FIG. 2 is in the architecture of FIG. 3 the output of the current path of transistor M1 is a current source I2, and not the output load, current load element I1.